ARM11 Processor Family
The ARM11™ processor family provides the engine that powers many smartphones in production today and is also widely used in consumer, home, and embedded applications. It delivers extreme low power and a range of performance from 350 MHz in small area designs up to 1 GHz in speed-optimized designs in 45 and 65 nm. ARM11 processor software is compatible with all previous generations of ARM processors, and introduces 32-bit SIMD for media processing, physically tagged caches to improve OS context switch performance,TrustZone for hardware-enforced security, and tightly coupled memories for real-time applications.
อ้างอิง : http://www.arm.com/products/processors/classic/arm11/index.php
Hazards
The VFP11 coprocessor incorporates full hazard detection with a
fully-interlocked pipeline protocol. No compiler scheduling is required to
avoid hazard conditions. The source and destination scoreboards process
interlocks caused by unavailable source or destination registers or by
unavailable data. The scoreboards stall instructions until all data operands
and destination registers are available before the instruction is issued to the
instruction pipeline.
The determination of hazards and interlock conditions is different
in full-compliance mode and RunFast mode. RunFast mode guarantees no bounce
conditions and has a less strict hazard detection mechanism, enabling
instructions to begin execution earlier than in full-compliance mode.
There are two VFP11 pipeline hazards:
- A data hazard is
a combination of instructions that creates the potential for operands to
be accessed in the wrong order.
- A Read-After-Write (RAW)
data hazard occurs when the pipeline creates the potential for an
instruction to read an operand before a prior instruction writes to it.
It is a hazard to the intended read-after-write operand access.
- A Write-After-Read (WAR)
data hazard occurs when the pipeline creates the potential for an
instruction to write to a register before a prior instruction reads it.
It is a hazard to the intended write-after-read operand access.
- A Write-After-Write (WAW)
data hazard occurs when the pipeline creates the potential for an
instruction to write to a register before a prior instruction writes to
it. It is a hazard to the intended write-after-write operand access.
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