WEEK9

Hazard (computer architecture)

• Data hazards

  Data hazards occur when instructions that exhibit data dependence modify data in different stages of a pipeline. Ignoring potential data hazards can result in race conditions (sometimes known as race hazards). There are three situations in which a data hazard can occur:
  1. read after write (RAW), a true dependency
  2. write after read (WAR), an anti-dependency
  3. write after write (WAW), an output dependency
  Consider two instructions i1 and i2, with i1 occurring before i2 in program order.

• Read After Write (RAW)

  (i2 tries to read a source before i1 writes to it) A read after write (RAW) data hazard refers to a situation where an instruction refers to a result that has not yet been calculated or retrieved. This can occur because even though an instruction is executed after a previous instruction, the previous instruction has not been completely processed through the pipeline.

  Example

  For example:
  i1. R2 <- R1 + R3
  i2. R4 <- R2 + R3
  The first instruction is calculating a value to be saved in register R2, and the second is going to use this value to compute a result for register R4. However, in a pipeline, when we fetch the operands for the 2nd operation, the results from the first will not yet have been saved, and hence we have a data dependency.
  We say that there is a data dependency with instruction i2, as it is dependent on the completion of instruction i1.

  Write After Read (WAR)

  (i2 tries to write a destination before it is read by i1) A write after read (WAR) data hazard represents a problem with concurrent execution.

  Example

  For example:
  i1. R4 <- R1 + R5
  i2. R5 <- R1 + R2
  If we are in a situation that there is a chance that i2 may be completed before i1 (i.e. with concurrent execution) we must ensure that we do not store the result of register R5 before i1 has had a chance to fetch the operands.

  Write After Write (WAW)

  (i2 tries to write an operand before it is written by i1) A write after write (WAW) data hazard may occur in a concurrent execution environment.

  Example

  For example:
  i1. R2 <- R4 + R7
  i2. R2 <- R1 + R3
  We must delay the WB (Write Back) of i2 until the execution of i1.

  Structural hazards

  A structural hazard occurs when a part of the processor's hardware is needed by two or more instructions at the same time. A canonical example is a single memory unit that is accessed both in the fetch stage where an instruction is retrieved from memory, and the memory stage where data is written and/or read from memory. They can often be resolved by separating the component into orthogonal units (such as separate caches) or bubbling the pipeline.

  Control hazards (branch hazards)

  Further information: branch (computer science)
  Branching hazards (also known as control hazards) occur with branches. On many instruction pipeline microarchitectures, the processor will not know the outcome of the branch when it needs to insert a new instruction into the pipeline (normally the fetch stage).
• อ้างอิง http://en.wikipedia.org/wiki/Hazard_(computer_architecture)